The increasing demand for communication bandwidth continually challenges the capability of copper-based interconnects, which causes more and more electronic manufacturers to turn towards using photonics. In particular, photo detector (PD) integration in the silicon (Si)-based CMOS process has been widely talked about and shows promise for usage in various equipment such as local area networks (LANs). Currently, most popular fabrication techniques include selective epitaxial (epi) growth of germanium (Ge) or germanium-silicon (Ge/Si) multi-layers to integrate a photo detector during the CMOS process. However, the growth rate associated with selective epitaxial growth is very low and due to the non-uniformity of the selective epitaxial window opening, the epi thickness may be varied at different locations and with different openings (normally referred to as loading effect). Further, at the same time, there can be facet formation during selective epitaxial growth.
A need therefore exists for methodology enabling a non-selective growth of a photo detector material integrated into the CMOS process, and the resulting device.